1. Field of the Invention
The present invention is related to NMOS-based integrated circuit (IC) output stages.
2. Related Art
As CMOS technology advances to the 0.1–0.2 μm range and beyond, supply voltages are scaled down accordingly. When voltage differences among the gate, source, and drain of a NMOS device exceed device ratings, the life of the device is significantly decreased. Therefore, a problem occurs when using NMOS devices in an IC output stage to interface relatively low supply voltage NMOS devices of an IC core circuit with relatively high supply voltage at the output stage.
In an example, the IC core circuit includes 0.13 μm NMOS devices that require a 1.2 V supply voltage, and the IC output stage requires a 3.3 V supply voltage. A level shifter coupled between the IC core circuit and output stage can be used to bridge the 1.2 V and 3.3 V power domains. But this approach is not advantageous because level shifters consume a significant amount of power, and combining 1.2 V IC core devices with 3.3 V output stage devices significantly increases processing cost.
What is needed, therefore, is a NMOS-based IC output stage to interface relatively low voltage NMOS devices in an IC core with relatively high voltages at the output stage, and more particularly, a system for protecting the NMOS devices in the IC output stage.